US 10,891,256 B2
Method and apparatus for a vector memory subsystem for use with a programmable mixed-radix DFT/IDFT processor
Yuanbin Guo, Mountain House, CA (US); and Hong Jik Kim, San Jose, CA (US)
Assigned to Cavium, LLC, Santa Clara, CA (US)
Filed by Cavium, LLC, Santa Clara, CA (US)
Filed on Feb. 11, 2019, as Appl. No. 16/272,470.
Application 16/272,470 is a continuation of application No. 15/292,015, filed on Oct. 12, 2016, granted, now 10,311,018.
Application 15/292,015 is a continuation in part of application No. 15/272,332, filed on Sep. 21, 2016, granted, now 10,210,135.
Claims priority of provisional application 62/279,345, filed on Jan. 15, 2016.
Claims priority of provisional application 62/274,686, filed on Jan. 4, 2016.
Claims priority of provisional application 62/274,062, filed on Dec. 31, 2015.
Prior Publication US 2019/0171613 A1, Jun. 6, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 17/14 (2006.01)
CPC G06F 15/8061 (2013.01) [G06F 9/30036 (2013.01); G06F 17/141 (2013.01); G06F 17/142 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable device configured to provide discrete Fourier transform (“DFT”) and inverse DFT (“IDFT”) operations for data processing, comprising:
a vector data path pipeline configured to generate scaled vector data by scaling input data received from a vector memory bank;
a finite state machine controller coupled to the vector data pipeline and configured to generate radix engine control signals in accordance a received index value; and
a programmable vector mixed-radix engine coupled to the finite state machine and capable of being configured in accordance with the radix engine control signals for facilitating producing a radix result in response to the scaled vector data.