US 10,891,190 B2
Flash memory and operation method thereof
Minyi Chen, Beijing (CN)
Assigned to GigaDevice Semiconductor (Beijing) Inc., Beijing (CN)
Filed by GigaDevice Semiconductor (Beijing) Inc., Beijing (CN)
Filed on Feb. 14, 2019, as Appl. No. 16/275,554.
Claims priority of application No. 2018 1 1644297 (CN), filed on Dec. 30, 2018.
Prior Publication US 2020/0210285 A1, Jul. 2, 2020
Int. Cl. G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 29/52 (2006.01); G11C 16/34 (2006.01); H01L 27/11524 (2017.01); G11C 11/56 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 29/52 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); H01L 27/11524 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for operating a flash memory, comprising:
reading out raw data from a plurality of memory cells;
correcting the raw data by using error correction code (ECC) data to obtain corrected data;
determining an address of a memory cell having a data loss error in the plurality of memory cells; and
programming the memory cell having the data loss error,
wherein the step of determining the address of the memory cell having the data loss error in the plurality of memory cells comprises: comparing the raw data and the corrected data, wherein a bit in the raw data corresponding to the memory cell having the data loss error is 1, and a bit in the corrected data corresponding to the memory cell having the data loss error is 0.