US 10,891,076 B1
Results processing circuits and methods associated with computational memory cells
Bob Haig, Sunnyvale, CA (US); Eli Ehrman, Sunnyvale, CA (US); Dan Ilan, Sunnyvale, CA (US); Patrick Chuang, Sunnyvale, CA (US); Chao-Hung Chang, Sunnyvale, CA (US); and Mu-Hsiang Huang, Sunnyvale, CA (US)
Assigned to GSI Technology, Inc., Sunnyvale, CA (US)
Filed by GSI Technology, Inc., Sunnyvale, CA (US)
Filed on Oct. 4, 2018, as Appl. No. 16/152,374.
Application 16/152,374 is a continuation in part of application No. 15/709,399, filed on Sep. 19, 2017.
Application 15/709,399 is a continuation in part of application No. 15/709,401, filed on Sep. 19, 2017, granted, now 10,249,362.
Application 15/709,401 is a continuation in part of application No. 15/709,379, filed on Sep. 19, 2017, granted, now 10,521,229.
Application 15/709,379 is a continuation in part of application No. 15/709,382, filed on Sep. 19, 2017, granted, now 10,725,777.
Application 15/709,382 is a continuation in part of application No. 15/709,385, filed on Sep. 19, 2017, granted, now 10,860,318.
Claims priority of provisional application 62/430,767, filed on Dec. 6, 2016.
Claims priority of provisional application 62/430,762, filed on Dec. 6, 2016.
Int. Cl. G11C 11/419 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0683 (2013.01); G11C 11/419 (2013.01)] 44 Claims
OG exemplary drawing
 
1. A processing array device, comprising:
a plurality of memory cells arranged in an array having a plurality of columns and a plurality of rows, each memory cell having a storage element wherein the array has a plurality of sections and each section has a plurality of bit line sections and a plurality of bit lines with one bit line per bit line section, wherein the memory cells in each bit line section are all connected to a single read bit line that generates a computation result and the plurality of bit lines in each section are distinct from the plurality of bit lines included in the other sections of the array;
each bit line section having a read storage device that captures the computation result;
each section having circuitry to logically combine the computation results captured by the bit line sections in the section;
each bit line section having circuitry that stores the combined computation results in one or more memory cells in the bit line section;
an RSP data line, connected to each bit line section, that communicates the combined computation result outside of the processing array device; and
wherein each section has an RSP data line that communicates the computation results for the plurality of bit line sections in the section, and wherein each bit line section has circuitry that generates a logical OR on the RSP data line of the computation results captured in all of the read storage devices in each of the bit line sections in the section and each bit line section stores the combined computation result.