US 10,890,620 B2
On-chip execution of in-system test utilizing a generalized test image
Milind Bhaiyyasaheb Sonawane, San Jose, CA (US); Shantanu K. Sarangi, Saratoga, CA (US); Sailendra Chadalavada, Saratoga, CA (US); Sumit Raj, Bangalore (IN); Rangavajjula Kameswara Naga Mahesh, Narasaraopet (IN); Jayesh Kumar Pandey, San Jose, CA (US); and Venkat Abilash Reddy Nerallapally, San Jose, CA (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on May 17, 2019, as Appl. No. 16/416,034.
Prior Publication US 2020/0363470 A1, Nov. 19, 2020
Int. Cl. G01R 31/28 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/3177 (2013.01) 18 Claims
OG exemplary drawing
 
1. A device comprising:
a first top controller for a system-on-a-chip;
a second top controller for a graphics processing unit;
the first top controller to retrieve test patterns for the second top controller from a test pattern storage memory, and to receive the test results from the second top controller;
the system-on-a-chip comprising a first plurality of functional logic blocks;
the graphics processing unit comprising a second plurality of functional logic blocks;
each of the functional logic blocks comprising a scan chain;
a plurality of first logic block controllers each associated with one or more of the first plurality of functional logic blocks and coordinated by the first top controller;
a plurality of second logic block controllers each associated with one or more of the second plurality of functional logic blocks and coordinated by the second top controller;
test logic to operate each top controller to load test patterns to the associated logic block controllers and to write test results back to the associated top controller after execution of the test patterns by the associated logic block controllers, the test patterns and test results both encoded in packet format; and
each logic block controller decoding and applying the test patterns to an associated scan chain.