US 12,193,342 B2
Manufacturing method of memory device
Chih-Wei Kuo, Tainan (TW); and Chung-Yi Chiu, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Aug. 28, 2023, as Appl. No. 18/239,108.
Application 18/239,108 is a continuation of application No. 17/372,528, filed on Jul. 12, 2021, granted, now 11,785,867.
Claims priority of application No. 202110651873.9 (CN), filed on Jun. 11, 2021.
Prior Publication US 2023/0413695 A1, Dec. 21, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/10 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/826 (2023.02) [H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10B 63/10 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A manufacturing method of a memory device, comprising:
forming a memory unit on a substrate, wherein the memory unit comprises:
a first electrode;
a second electrode disposed above the first electrode in a vertical direction; and
a memory material layer disposed between the first electrode and the second electrode in the vertical direction; and
forming a first spacer layer on a sidewall of the memory unit, wherein the first spacer layer comprises:
a first portion disposed on a sidewall of the first electrode;
a second portion disposed on a sidewall of the second electrode, wherein a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction; and
a third portion disposed above the memory unit in the vertical direction and connected with the second portion.