US 12,193,341 B2
Low resistance via contacts in a memory device
Giulio Albini, Draper, UT (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 28, 2022, as Appl. No. 17/875,691.
Application 17/875,691 is a division of application No. 16/832,324, filed on Mar. 27, 2020, granted, now 11,430,950.
Prior Publication US 2022/0367799 A1, Nov. 17, 2022
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/826 (2023.02) [H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an array of memory cells;
a via that extends through a dielectric material in a first direction, the dielectric material disposed between the array of memory cells and the via;
a first material above the array of memory cells and the dielectric material, a portion of the via protruding from the dielectric material by a height that is greater than a thickness of the first material above the array of memory cells, wherein a portion of the first material that is above the dielectric material and in contact with the portion of the via that protrudes from the dielectric material has a length in the first direction equal to the height by which the portion of the via protrudes from the dielectric material; and
an access line above the first material, the access line extending from above the array of memory cells to above the via, and the access line in contact with a top surface of the first material and a top surface of the via, wherein, in a second direction perpendicular to the first direction, the portion of the first material is between a sidewall of the via and a portion of the access line.