CPC H10N 50/01 (2023.02) [H10B 61/22 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
1. A structure having a memory device region and a logic device region, the structure comprising:
a first metal layer extending across an interface between the memory device region and the logic device region;
a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
a first dielectric layer over the dielectric barrier layer in the memory device region;
multiple magnetic tunneling junction (MTJ) devices in the memory device region, wherein the MTJ devices are disposed over the first metal layer, the dielectric barrier layer, and the first dielectric layer;
a second dielectric layer in the memory device region, wherein the second dielectric layer is disposed over the first dielectric layer and the MTJ devices;
an extreme low-k dielectric layer over and in physical contact with the dielectric barrier layer in the logic device region and in physical contact with a sidewall of the first and second dielectric layers, wherein a portion of the extreme low-k dielectric layer is directly over the second dielectric layer in the memory device region; and
a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.
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