US 12,193,244 B2
Memory device and semiconductor device
Yutaka Shionoiri, Isehara (JP); Hiroyuki Miyake, Atsugi (JP); and Kiyoshi Kato, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 19, 2022, as Appl. No. 17/891,248.
Application 17/891,248 is a continuation of application No. 17/061,920, filed on Oct. 2, 2020, granted, now 11,424,246.
Application 17/061,920 is a continuation of application No. 15/292,362, filed on Oct. 13, 2016, granted, now 10,797,054, issued on Oct. 6, 2020.
Application 15/292,362 is a continuation of application No. 12/976,340, filed on Dec. 22, 2010, granted, now 9,472,559, issued on Oct. 18, 2016.
Claims priority of application No. 2009-297140 (JP), filed on Dec. 28, 2009.
Prior Publication US 2022/0415893 A1, Dec. 29, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 27/13 (2006.01); H10B 41/70 (2023.01); H10B 69/00 (2023.01); H10B 99/00 (2023.01); G11C 16/04 (2006.01)
CPC H10B 99/00 (2023.02) [H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 27/13 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H10B 41/70 (2023.02); H10B 69/00 (2023.02); G11C 16/0433 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor;
a second transistor; and
a capacitor element,
wherein the first transistor comprises a first oxide semiconductor layer between a first conductive layer and a second conductive layer,
wherein the second transistor comprises a second oxide semiconductor layer,
wherein the first oxide semiconductor layer overlaps with the first conductive layer,
wherein the second conductive layer overlaps with the first oxide semiconductor layer,
wherein each of a third conductive layer and a fourth conductive layer is over and in contact with the first oxide semiconductor layer,
wherein the second conductive layer is electrically connected to one of a source electrode and a drain electrode of the second transistor through a contact hole,
wherein in a channel length direction of the first transistor, a maximum width of the second conductive layer is larger than a maximum width of the first oxide semiconductor layer,
wherein the third conductive layer comprises a first region which overlaps with the first oxide semiconductor layer and a second region which does not overlap with the first oxide semiconductor layer,
wherein the second conductive layer comprises a third region which overlaps with the second region of the third conductive layer,
wherein the third region of the second conductive layer is configured to be a first electrode of the capacitor element,
wherein the second region of the third conductive layer is configured to be a second electrode of the capacitor element,
wherein in the channel length direction of the first transistor, a maximum width of the second region of the third conductive layer is larger than a maximum width of the first region of the third conductive layer, wherein the second oxide semiconductor layer and the contact hole do not overlap with each other, and
wherein a signal is supplied to the other of the source electrode and the drain electrode of the second transistor.