US 12,193,236 B2
Memory device and electronic device
Hitoshi Kunitake, Isehara (JP); Satoru Ohshita, Atsugi (JP); Kazuki Tsuda, Atsugi (JP); and Tatsuya Onuki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/772,280
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Nov. 13, 2020, PCT No. PCT/IB2020/060677
§ 371(c)(1), (2) Date Apr. 27, 2022,
PCT Pub. No. WO2021/105811, PCT Pub. Date Jun. 3, 2021.
Claims priority of application No. 2019-213485 (JP), filed on Nov. 26, 2019.
Prior Publication US 2022/0375956 A1, Nov. 24, 2022
Int. Cl. H10B 43/40 (2023.01); G11C 16/08 (2006.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [G11C 16/08 (2013.01); H10B 43/27 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first layer;
a second layer; and
a third layer,
wherein a decoder is provided in the first layer,
wherein a memory cell portion is provided in the second layer,
wherein a circuit is provided in the third layer,
wherein the circuit is configured to control the decoder and the memory cell portion,
wherein the decoder is configured to select or deselect part of the memory cell portion,
wherein at least part of the second layer is provided to be stacked above the third layer, and
wherein at least part of the first layer is provided to be stacked above the second layer.