US 12,193,232 B2
Semiconductor device including separation patterns and an electronic system
Joongshik Shin, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 29, 2021, as Appl. No. 17/488,576.
Claims priority of application No. 10-2021-0012103 (KR), filed on Jan. 28, 2021.
Prior Publication US 2022/0238550 A1, Jul. 28, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 43/10 (2023.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a horizontal wiring layer;
a stack structure comprising a plurality of mold layers and a plurality of wiring layers alternately stacked on the horizontal wiring layer;
a plurality of channel structures extending through the stack structure; and
a plurality of separation patterns extending through the stack structure,
wherein each of the plurality of separation patterns comprises a plurality of first areas and a plurality of second areas adjacent to the plurality of first areas, wherein each of the plurality of first areas has a smaller width than each of the plurality of second areas,
wherein:
the plurality of channel structures extends into the horizontal wiring layer;
each of the plurality of separation patterns comprises a plurality of downward protrusions extending into the horizontal wiring layer; and
a distance between a lowermost end of each of the plurality of downward protrusions and a lower surface of the horizontal wiring layer is smaller than a distance between a lowermost end of each of the plurality of channel structures and the lower surface of the horizontal wiring layer.