	US 12,193,231 B2
	Fabricating three-dimensional semiconductor structures
Soo Doo Chae, Albany, NY (US); Karthikeyan Pillai, Albany, NY (US); Lior Huli, Albany, NY (US); Na Young Bae, Albany, NY (US); and Hojin Kim, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Sep. 10, 2021, as Appl. No. 17/472,213.
Claims priority of provisional application 63/089,110, filed on Oct. 8, 2020.
Prior Publication US 2022/0115399 A1, Apr. 14, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 43/10 (2023.01)

CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02)]

20 Claims

1. A method of fabricating a device, the method comprising:

forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material, each layer of the first spin-on material and the second spin-on material formed by spin-on deposition;

etching first openings through the layer stack;

filling the first openings with a third material;

etching second openings through the layer stack;

removing the first spin-on material from the layer stack;

replacing the first spin-on material with a fourth material, the fourth material being a metal-containing material;

removing the second spin-on material from the layer stack; and

replacing the second spin-on material with a fifth material, the fifth material being an insulating material.