US 12,193,226 B2
Nonvolatile semiconductor memory device and method for manufacturing same
Keiichi Sawa, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 30, 2023, as Appl. No. 18/344,957.
Application 18/344,957 is a continuation of application No. 17/224,356, filed on Apr. 7, 2021, granted, now 11,737,262.
Application 17/224,356 is a continuation of application No. 16/601,748, filed on Oct. 15, 2019, granted, now 11,011,532, issued on May 18, 2021.
Application 16/601,748 is a continuation of application No. 15/956,823, filed on Apr. 19, 2018, granted, now 10,490,563, issued on Nov. 26, 2019.
Application 15/956,823 is a continuation of application No. 15/014,112, filed on Feb. 3, 2016, granted, now 9,978,765, issued on May 22, 2018.
Application 15/014,112 is a continuation of application No. 13/780,150, filed on Feb. 28, 2013, granted, now 9,287,388, issued on Mar. 15, 2016.
Claims priority of application No. 2012-089421 (JP), filed on Apr. 10, 2012.
Prior Publication US 2023/0354596 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01)
CPC H10B 41/27 (2023.02) [H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/7889 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising:
a plurality of first memory cells stacked in a first direction and electrically connected in series;
a plurality of second memory cells stacked in the first direction and electrically connected in series, the first memory cells and the second memory cells being arranged in a second direction orthogonal to the first direction; and
a connection member provided above a substrate via an insulating layer and below the first memory cells and the second memory cells, the connection member being electrically connected to one end of the first memory cells and one end of the second memory cells,
the first memory cells including:
a first semiconductor body extending in the first direction, the first semiconductor body including one end corresponding to the one end of the first memory cells, and
a plurality of first control electrodes opposed to a side surface of the first semiconductor body via first charge retaining portions respectively, the first control electrodes being alternately stacked in the first direction with a plurality of first insulators therebetween,
the second memory cells including:
a second semiconductor body extending in the first direction, the second semiconductor body including one end corresponding to the one end of the second memory cells, and
a plurality of second control electrodes opposed to a side surface of the second semiconductor body via second charge retaining portions respectively, the second control electrodes being alternately stacked in the first direction with a plurality of second insulators therebetween,
the one end of the first semiconductor body and the one end of the second semiconductor body being coupled to the connection member and being disconnected from each other in the second direction, and
the connection member including TiN.