CPC H10B 12/34 (2023.02) [H10B 12/053 (2023.02)] | 19 Claims |
1. A semiconductor device, comprising:
a substrate including an active region defined by an isolation layer;
a buried gate structure provided in a trench formed in the substrate; and
a first doped region and a second doped region formed in the active region and separated by the trench,
wherein the buried gate structure comprises:
a gate dielectric layer conformally covering the trench; and
a gate electrode including a first portion partially filling the trench on the gate dielectric layer and a second portion formed on the first portion,
wherein the second portion comprises a material included in the first portion and dopants including phosphorous (P), germanium (Ge), or a combination thereof,
wherein the first portion does not laterally overlap with the first doped region and the second doped region, and all or a part of the second portion laterally overlaps with the first doped region and the second doped region, and
wherein sidewalls of the first and the second portions are aligned with each other, and the first portion has a height greater than that of the second portion.
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