US 12,193,210 B2
Method of forming a wiring and method of manufacturing a semiconductor device using the same
Hyunchul Lee, Hwaseong-si (KR); Kijeong Kim, Hwaseong-si (KR); Jongcheon Kim, Seoul (KR); Donghwi Shin, Yongin-si (KR); and Hyunsil Hong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 13, 2022, as Appl. No. 17/719,622.
Claims priority of application No. 10-2021-0098353 (KR), filed on Jul. 27, 2021.
Prior Publication US 2023/0035456 A1, Feb. 2, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01)
CPC H10B 12/0335 (2023.02) [H01L 21/0274 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H10B 12/482 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a wiring, the method comprising:
forming an insulating interlayer on a substrate, the insulating interlayer including a low-k dielectric material;
forming a first etching mask on the insulating interlayer;
performing a first etching process using the first etching mask to form a first opening through the insulating interlayer;
removing the first etching mask;
forming a protection pattern on a bottom and a side of the first opening;
forming a second etching mask on the protection pattern and the insulating interlayer;
performing a second etching process using the second etching mask to form a second opening through the insulating interlayer;
removing the second etching mask;
removing the protection pattern; and
forming the wiring in each of the first and second openings.