CPC H10B 10/18 (2023.02) [G11C 11/418 (2013.01); H10B 10/12 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a first memory array;
a first isolation cell abutting a first side of the first memory array;
a first edge cell array abutting a second side, opposite to the first side, of the first memory array, wherein a first width of the first isolation cell is different from a second width of the first edge cell array;
a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell;
a second edge cell array, wherein the second memory array is sandwiched between the second edge cell array and the first isolation cell; and
a plurality of first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell.
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