US 12,193,205 B2
Memory device and manufacturing method
Kuo-Hung Lo, Hsinchu (TW); Feng-Ming Chang, Hsinchu County (TW); and Ying-Hsiu Kuo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 5, 2023, as Appl. No. 18/313,041.
Application 18/313,041 is a continuation of application No. 17/698,929, filed on Mar. 18, 2022, granted, now 11,683,924.
Application 17/698,929 is a continuation of application No. 17/098,269, filed on Nov. 13, 2020, granted, now 11,282,842, issued on Mar. 22, 2022.
Application 17/098,269 is a continuation of application No. 16/417,477, filed on May 20, 2019, granted, now 10,840,251, issued on Nov. 17, 2020.
Claims priority of provisional application 62/750,779, filed on Oct. 25, 2018.
Prior Publication US 2023/0276608 A1, Aug. 31, 2023
Int. Cl. H10B 10/00 (2023.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01)
CPC H10B 10/12 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A static random access memory (SRAM) device, comprising:
a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate; and
a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of the substrate,
wherein the first gate and the second gate are aligned to each other on a cross-sectional line along a first direction,
wherein a boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.