US 12,193,150 B2
Conductive features on system-in-package surfaces
Ali N. Ergun, Sunnyvale, CA (US); Bilal Mohamed Ibrahim Kani, Singapore (SG); Chang Liu, San Jose, CA (US); Ethan L. Huwe, Davis, CA (US); Jeffrey J. Terlizzi, San Francisco, CA (US); Jerzy S. Guterman, Sunnyvale, CA (US); Jue Wang, San Jose, CA (US); Kishore N. Renjan, Singapore (SG); Kyusang Kim, Singapore (SG); Lan H. Hoang, San Jose, CA (US); Mandar S. Painaik, Cupertino, CA (US); Manoj Vadeentavida, Singapore (SG); Sarah B. Gysbers, Santa Clara, CA (US); Takayoshi Katahira, San Jose, CA (US); and Zhiqi Wang, Shanghai (CN)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 3, 2022, as Appl. No. 17/832,346.
Claims priority of provisional application 63/243,892, filed on Sep. 14, 2021.
Prior Publication US 2023/0078536 A1, Mar. 16, 2023
Int. Cl. H05K 1/02 (2006.01); H01L 21/56 (2006.01); H01L 21/68 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/42 (2006.01); H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H01Q 1/22 (2006.01); H01Q 1/36 (2006.01); H01Q 1/38 (2006.01); H01Q 1/48 (2006.01); H01Q 1/50 (2006.01); H01Q 1/52 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01)
CPC H05K 1/0243 (2013.01) [H01Q 1/22 (2013.01); H01Q 1/36 (2013.01); H05K 1/11 (2013.01); H05K 2201/10098 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A system-in-package module comprising:
a board having a top surface;
an integrated circuit attached to a first plurality of contacts on the top surface of the board;
a first vertical interconnect pin connected to a first contact on the top surface of the board;
a second vertical interconnect pin connected to a second contact on the top surface of the board;
an encapsulation having a curved top surface and positioned on the top surface of the board, the encapsulation over the integrated circuit and at least substantially around the first vertical interconnect pin and the second vertical interconnect pin; and
an antenna on the top surface of the encapsulation, such that the encapsulation is between the antenna and the top surface of the board, the antenna connected to the first vertical interconnect pin and the second vertical interconnect pin.