CPC H04W 52/146 (2013.01) [H04W 52/242 (2013.01); H04W 52/365 (2013.01); H04W 52/367 (2013.01); H04W 72/0446 (2013.01); H04W 72/23 (2023.01)] | 18 Claims |
1. A processor configured to perform operations comprising:
receiving a frequency domain resource allocation (FDRA) configuration from a network, the FDRA configuration comprising at least one of a first FDRA mode or a second FDRA mode, wherein the first FDRA mode utilizes an FDRA unit comprising a set of consecutive resource blocks (RBs) and the second FDRA mode utilizes an FDRA unit comprising a set of interlaced RBs, wherein the FDRA unit for the first mode comprises K consecutive RBs, wherein K is a function of regulatory requirements for a maximum power spectral density (PSD) and a subcarrier spacing (SCS) to be used for the UL transmission;
when both of the first and second FDRA modes are configured, receiving a signal indicating which one of the two FDRA modes are to be used for an uplink (UL) transmission; and
performing the UL transmission in accordance with the indicated FDRA mode.
|