US 12,192,665 B2
Solid-state imaging device and imaging system
Masahiro Kobayashi, Tokyo (JP); and Mineo Shimotsusa, Machida (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Jul. 30, 2021, as Appl. No. 17/390,605.
Application 17/390,605 is a continuation of application No. 16/393,662, filed on Apr. 24, 2019, granted, now 11,102,440.
Application 16/393,662 is a continuation of application No. 15/868,804, filed on Jan. 11, 2018, granted, now 10,304,899, issued on Jan. 23, 2019.
Application 15/868,804 is a continuation of application No. 14/992,234, filed on Jan. 11, 2016, granted, now 9,899,449, issued on Feb. 20, 2018.
Application 14/992,234 is a continuation of application No. 13/807,084, granted, now 9,252,169, issued on Feb. 2, 2016, previously published as PCT/JP2011/003570, filed on Jun. 22, 2011.
Claims priority of application No. 2010-149484 (JP), filed on Jun. 30, 2010.
Prior Publication US 2021/0360186 A1, Nov. 18, 2021
Int. Cl. H04N 25/79 (2023.01); H01L 27/02 (2006.01); H01L 27/146 (2006.01); H10K 65/00 (2023.01)
CPC H04N 25/79 (2023.01) [H01L 27/0255 (2013.01); H01L 27/0296 (2013.01); H01L 27/146 (2013.01); H01L 27/14636 (2013.01); H01L 27/1464 (2013.01); H01L 27/14685 (2013.01); H01L 27/14689 (2013.01); H10K 65/00 (2023.02); H01L 27/14645 (2013.01)] 42 Claims
OG exemplary drawing
 
1. A device comprising:
a first semiconductor substrate which includes a photoelectric conversion element;
a second semiconductor substrate which includes a transistor; and
a wiring structure which is arranged between the first semiconductor substrate and the second semiconductor substrate,
wherein the first semiconductor substrate is provided with an opening,
wherein the second semiconductor substrate includes semiconductor regions and an insulating member,
wherein the semiconductor regions include a first semiconductor region and a second semiconductor region separated from the first semiconductor region by the insulating member, and
wherein the opening and at least one of the insulating member, the first semiconductor region and the second semiconductor regions overlap each other, or the opening and a poly silicon portion arranged between the wiring structure and the second semiconductor substrate overlap each other.