CPC H04N 19/625 (2014.11) [H04N 19/129 (2014.11); H04N 19/176 (2014.11); H04N 19/70 (2014.11)] | 11 Claims |
1. An apparatus for decoding a video signal, comprising:
a memory configured to store the video signal; and
a processor coupled to the memory,
wherein the processor is configured to:
check whether a transform skip is applied to a current block;
obtain a transform index specifying which transform kernels are applied along horizontal and vertical directions of the current block based on that the transform skip is not applied to the current block;
determine a non-zero region based on the transform kernels specified by the transform index and a width and/or a height of the current block, wherein the transform kernels correspond to at least one of predefined transform types including DCT2, DST7 and DCT8;
perform an inverse transform on the non-zero region based on the transform kernels specified by the transform index to generate residual samples of the current block; and
generate reconstructed samples of the current block based on the residual samples.
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