CPC H04N 19/31 (2014.11) [H04N 19/107 (2014.11); H04N 19/184 (2014.11); H04N 19/187 (2014.11); H04N 19/70 (2014.11)] | 20 Claims |
18. An apparatus comprising:
processing circuitry; and
memory coupled with the processing circuitry, wherein the memory includes instructions that when executed by the processing circuitry causes the apparatus to:
decode a picture A0 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T0 are decoded from the bitstream for picture A0;
decode a picture B0 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T1 are decoded from the bitstream for picture B0, wherein B represents a higher temporal layer than A, and wherein T1 represents a later output than T0, and wherein picture B0 uses picture A0 for Inter prediction;
decode a picture A1 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for picture A1, wherein T2 represents a later output than T1, and wherein picture A1 uses picture A0 for Inter prediction;
decode a picture B1 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T3 are decoded from the bitstream for picture B1, wherein T3 represents a later output than T2, and wherein picture B1 uses picture A1 and picture B0 for Inter prediction; and
output pictures B0 and B1 but not output pictures A0 or A1.
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