US 12,192,466 B2
Video coding apparatus and video decoding apparatus
Tomohiro Ikai, Sakai (JP); Tomoko Aono, Sakai (JP); Takeshi Chujoh, Sakai (JP); Yukinobu Yasugi, Sakai (JP); and Eiichi Sasaki, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Filed by Sharp Kabushiki Kaisha, Osaka (JP)
Filed on Sep. 13, 2023, as Appl. No. 18/367,527.
Application 18/367,527 is a continuation of application No. 17/429,024, granted, now 11,818,355, previously published as PCT/JP2020/004869, filed on Feb. 7, 2020.
Claims priority of application No. 2019-021630 (JP), filed on Feb. 8, 2019; and application No. 2019-057031 (JP), filed on Mar. 25, 2019.
Prior Publication US 2024/0007635 A1, Jan. 4, 2024
Int. Cl. H04N 19/13 (2014.01); H04N 19/174 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/13 (2014.11) [H04N 19/174 (2014.11); H04N 19/70 (2014.11)] 3 Claims
OG exemplary drawing
 
1. A video decoding apparatus for decoding a picture, the video decoding apparatus comprising:
a header decoding circuit that decodes an enabled flag, indicating whether a synchronization process for a Context-Adaptive Binary Arithmetic Coding (CABAC) is performed, in a parameter set, wherein
the header decoding circuit derives a raster scan Coding Tree Unit (CTU) address list equal to a sum of (a) a first CTU address in a tile group and (b) a product of a second CTU address of the tile group and a variable for a picture size,
the first CTU address and the second CTU address specify a location in CTU units,
the header decoding circuit derives a variable specifying a number of entry points based on a value of the enabled flag and the raster scan CTU address list,
the header decoding circuit decodes a first syntax element and a second syntax element, in a case that a value of the variable is greater than 0,
the first syntax element plus one specifies an entry point offset, and
the second syntax element plus one specifies the number of bits of the first syntax element.