| CPC H04N 19/105 (2014.11) [H04N 19/117 (2014.11); H04N 19/12 (2014.11); H04N 19/124 (2014.11); H04N 19/147 (2014.11); H04N 19/176 (2014.11); H04N 19/45 (2014.11); H04N 19/46 (2014.11); H04N 19/593 (2014.11); H04N 19/619 (2014.11); H04N 19/625 (2014.11)] | 2 Claims |
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1. An image decoding device for decoding a signal encoded by block-dividing a frame constituting a moving image, the image decoding device comprising:
a predicter circuitry configured to generate an inter predicted block corresponding to a decoding target block by an inter prediction that performs signal prediction for each pixel signal of the decoding target block;
a weighted average filter processor configured to perform a weighted average filter process to the inter predicted block before performing a block configuring process that generates a decoded block, wherein the weighted average filter processor is configured to modify the inter predicted block by using weighting factors and decoded neighboring pixels neighboring to the inter predicted block;
an inverse orthogonal transformer comprising:
an inverse transformation selection applier circuitry configured to selectively apply a plurality of types of inverse transformation processes according to a sub-block division to transformation coefficients of a prediction residual block that has been sub-block-divided by an image encoding side, and to generate a sub-block of the prediction residual block; and
a block reconfigurer circuitry configured to generate the prediction residual block corresponding to the decoding target block based on the sub-block of the prediction residual block, wherein the sub-block of the prediction residual block is a part of the prediction residual block corresponding to the decoding target block; and
the image decoding device further comprises a decoded image generator configured to generate and output the decoded block by receiving, as inputs: the inter predicted block and an output of the block reconfigurer circuitry.
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