US 12,192,315 B2
Monitoring circuit of phase locked loop and operating method thereof
Dokyung Lim, Seoul (KR); Sounghun Shin, Anyang-si (KR); Wooseok Kim, Suwon-si (KR); Wonsik Yu, Anyang-si (KR); and Chanyoung Jeong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 13, 2022, as Appl. No. 17/943,932.
Claims priority of application No. 10-2021-0124265 (KR), filed on Sep. 16, 2021.
Prior Publication US 2023/0082930 A1, Mar. 16, 2023
Int. Cl. H03D 3/24 (2006.01); H04L 7/033 (2006.01); H04L 43/087 (2022.01)
CPC H04L 7/033 (2013.01) [H04L 43/087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A monitoring circuit comprising:
a phase locked loop configured to generate an output signal by dividing an input signal based on a plurality of dividers;
a plurality of dividing monitoring circuits, each dividing monitoring circuit being associated with a respective divider of the plurality of dividers and configured to receive a dividing input signal and a dividing output signal corresponding to the respective divider and to output a dividing error signal based on a dividing ratio range and a dividing ratio of the dividing output signal to the dividing input signal corresponding to the respective divider; and
a jitter monitoring circuit configured to output a jitter error signal based on jitter of a signal generated in the phase locked loop and a jitter error range set in a calibration mode.