US 12,192,123 B2
Datapath for multiple tenants
Ronghua Zhang, San Jose, CA (US); Yong Wang, San Jose, CA (US); Teemu Koponen, San Francisco, CA (US); and Xinhua Hong, Milpitas, CA (US)
Assigned to Nicira, Inc., Palo Alto, CA (US)
Filed by Nicira, Inc., Palo Alto, CA (US)
Filed on Jul. 14, 2023, as Appl. No. 18/222,385.
Application 18/222,385 is a continuation of application No. 17/732,469, filed on Apr. 28, 2022, granted, now 11,706,159.
Application 17/732,469 is a continuation of application No. 16/885,189, filed on May 27, 2020, granted, now 11,343,204, issued on May 24, 2022.
Application 16/885,189 is a continuation of application No. 16/447,793, filed on Jun. 20, 2019, granted, now 10,700,997, issued on Jun. 30, 2020.
Application 16/447,793 is a continuation of application No. 14/929,431, filed on Nov. 2, 2015, granted, now 10,341,257, issued on Jul. 2, 2019.
Claims priority of provisional application 62/110,061, filed on Jan. 30, 2015.
Prior Publication US 2023/0362105 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/25 (2022.01); H04L 12/46 (2006.01); H04L 12/66 (2006.01); H04L 41/0654 (2022.01); H04L 41/14 (2022.01); H04L 41/5041 (2022.01); H04L 43/08 (2022.01); H04L 43/106 (2022.01); H04L 45/00 (2022.01); H04L 45/02 (2022.01); H04L 45/122 (2022.01); H04L 45/302 (2022.01); H04L 45/42 (2022.01); H04L 45/44 (2022.01); H04L 45/586 (2022.01); H04L 45/64 (2022.01); H04L 45/74 (2022.01); H04L 45/745 (2022.01); H04L 47/19 (2022.01); H04L 49/00 (2022.01); H04L 49/354 (2022.01); H04L 49/90 (2022.01); H04L 61/2585 (2022.01); H04L 67/1001 (2022.01); H04L 67/1038 (2022.01); H04L 67/568 (2022.01); H04L 67/63 (2022.01); H04L 69/321 (2022.01); H04L 69/326 (2022.01); H04L 69/329 (2022.01); H04L 41/50 (2022.01); H04L 45/28 (2022.01); H04L 61/103 (2022.01); H04L 61/2503 (2022.01); H04L 67/1095 (2022.01); H04L 101/663 (2022.01)
CPC H04L 49/25 (2013.01) [H04L 12/4633 (2013.01); H04L 12/4654 (2013.01); H04L 12/66 (2013.01); H04L 41/0654 (2013.01); H04L 41/145 (2013.01); H04L 41/5041 (2013.01); H04L 43/08 (2013.01); H04L 43/106 (2013.01); H04L 45/02 (2013.01); H04L 45/122 (2013.01); H04L 45/306 (2013.01); H04L 45/42 (2013.01); H04L 45/44 (2013.01); H04L 45/586 (2013.01); H04L 45/64 (2013.01); H04L 45/72 (2013.01); H04L 45/74 (2013.01); H04L 45/742 (2013.01); H04L 45/745 (2013.01); H04L 47/19 (2013.01); H04L 49/3009 (2013.01); H04L 49/3063 (2013.01); H04L 49/354 (2013.01); H04L 49/9068 (2013.01); H04L 61/2585 (2013.01); H04L 67/1001 (2022.05); H04L 67/1038 (2013.01); H04L 67/568 (2022.05); H04L 67/63 (2022.05); H04L 69/321 (2013.01); H04L 69/326 (2013.01); H04L 69/329 (2013.01); H04L 2012/4629 (2013.01); H04L 41/5077 (2013.01); H04L 45/22 (2013.01); H04L 45/28 (2013.01); H04L 45/38 (2013.01); H04L 61/103 (2013.01); H04L 61/2503 (2013.01); H04L 67/1095 (2013.01); H04L 2101/663 (2022.05)] 20 Claims
OG exemplary drawing
 
1. A method for processing a data message received by a gateway computing device that processes data messages sent between (i) a provider network on which one or more logical networks are implemented and (ii) an external physical network, the method comprising:
determining whether the data message has a valid corresponding entry in a cache stored by the gateway computing device;
when the data message does not have a valid corresponding cache entry:
executing a set of pipeline stages to determining a next destination of the received data message, wherein each stage of the set of pipeline stages (i) corresponds to a logical forwarding element (LFE) of one of the logical networks and (ii) produces a set of cache entry synthesizing instructions based on processing of the data message according to configuration for the corresponding LFE; and
synthesizing a new cache entry based on the sets of cache entry synthesizing instructions and storing the new cache entry in the cache for use in processing subsequent data messages belonging to a same data message flow as the received data message.