| CPC H04L 49/103 (2013.01) [H04L 45/122 (2013.01); H04L 47/30 (2013.01); H04L 49/9005 (2013.01); H04L 49/9047 (2013.01)] | 14 Claims |
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1. A device, comprising:
one or more ports, to communicate packets over a network;
a packet processor, to process the packets using a plurality of queues; and
a memory management circuit, to:
maintain a shared buffer in a memory, and adaptively allocate memory resources from the shared buffer to the queues;
maintain in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by one or more of the queues;
identify, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is:
(i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and
(ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool; and
allocate memory resources to the identified queue from the shared-reserve memory pool.
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