CPC H04L 27/26532 (2021.01) [H04L 25/0202 (2013.01)] | 30 Claims |
1. An apparatus configured for wireless communications, comprising:
one or more memories comprising processor-executable instructions; and
one or more processors configured to execute the processor-executable instructions and cause the apparatus to:
send an indication that the apparatus is capable of supporting lattice reduction (LR) demodulation;
receive a modulated signal; and
receive a first LR transformation matrix to be used for demodulating the modulated signal.
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