CPC H04L 1/0071 (2013.01) [H03M 13/15 (2013.01); H04L 1/0003 (2013.01); H04L 1/0009 (2013.01); H04L 1/0059 (2013.01); H04L 1/22 (2013.01); H04L 5/0007 (2013.01); H04L 27/0008 (2013.01); H04L 27/36 (2013.01); H04L 27/38 (2013.01); H04L 27/2647 (2013.01)] | 16 Claims |
1. A circuit comprising:
reception circuitry, which, in operation, controls receiving a combined signal transmitted from at least an antenna; and
demodulation circuitry, which, in operation, controls demodulating the combined signal,
wherein the combined signal is generated by generating two codeword signals by encoding data, by generating a first mapping signal and a second mapping signal by mapping each of the two codeword signals on at least one of an in-phase/quadrature phase (I-Q) plane corresponding to a quadrature phase-shift keying (QPSK) scheme and an I-Q plane corresponding to a 16 quadrature amplitude modulation (16QAM) scheme, by arranging the second mapping signal by using an equation having an angle that is not equal to zero, and by combining the first mapping signal and a phase-rotated second mapping signal arranged using the equation to generate a combined signal; and
wherein a first codeword of the two codeword signals includes a first cyclic redundancy check (CRC) bits relating to the first codeword, and a second codeword of the two codeword signals includes a second cyclic redundancy check (CRC) bits relating to the second codeword, and
wherein the combined signal includes at least one data of the first codeword and one data of the second codeword on each symbol.
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