CPC H04B 7/0456 (2013.01) [H04B 7/0632 (2013.01); H04B 7/068 (2013.01); H04B 7/0689 (2013.01); H04B 7/0691 (2013.01); H04B 7/0871 (2013.01); H04B 7/0874 (2013.01); H04J 13/00 (2013.01); H04L 5/0023 (2013.01); H04L 5/0051 (2013.01); H04W 72/04 (2013.01)] | 5 Claims |
1. An integrated circuit, comprising:
determination circuitry, which, in operation, controls determining one or more antenna ports used for transmission of reference signals; and
transmission circuitry, which, in operation, controls transmitting downlink control information including Demodulation Reference Signal (DMRS) antenna port information indicating the one or more antenna ports,
wherein the one or more antenna ports are selected from a plurality of candidates including a first antenna port pair, a second antenna port pair, and a single antenna port,
wherein the first antenna port pair is an antenna port pair in which reference signals of a first antenna port and a second antenna port are assigned in different resource elements and power boosting is applied to the reference signals, the second antenna port pair is an antenna port pair in which the reference signals of the first antenna port and a third antenna port are assigned in same resource elements and power boosting is not applied to the reference signals, and the single antenna port is the second antenna port.
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