US 12,191,893 B2
Seemingly monolithic interface between separate integrated circuit die
David W. Mendel, Sunnyvale, CA (US); Jeffrey Erik Schulz, Milpitas, CA (US); Keith Duwel, San Jose, CA (US); Huy Ngo, San Jose, CA (US); and Jakob Raymond Jones, San Jose, CA (US)
Assigned to ALTERA CORPORATION, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,556.
Application 17/385,556 is a continuation of application No. 16/585,934, filed on Sep. 27, 2019, granted, now 11,075,648.
Application 16/585,934 is a continuation of application No. 15/392,209, filed on Dec. 28, 2016, granted, now 10,439,639, issued on Oct. 8, 2019.
Prior Publication US 2022/0190843 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 9/00 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); H03K 19/17736 (2020.01)
CPC H03M 9/00 (2013.01) [G06F 1/12 (2013.01); G06F 13/4282 (2013.01); H03K 19/17744 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a sampling circuitry to sample a first portion of a plurality of signals more often than a second portion of the plurality of signals; and
a transmitter to generate a serial signal based on the plurality of signals and transmit the serial signal, wherein a frame of the serial signal comprises a first time slot comprising a flag bit indicating a state of a plurality of bits of the first time slot, a first plurality of time slots that comprise the first portion of the plurality of signals, and a second plurality of time slots that comprise the second portion of the plurality of signals.