US 12,191,885 B1
Early detection of single bit error on address and data
Karthik Thucanakkenpalayam Sundararajan, Fremont, CA (US); and Geogy Jacob, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Sep. 27, 2022, as Appl. No. 17/953,689.
Int. Cl. H03M 13/15 (2006.01); H03M 13/00 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); H03M 13/11 (2006.01); H03M 13/45 (2006.01)
CPC H03M 13/159 (2013.01) [H03M 13/611 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); H03M 13/1111 (2013.01); H03M 13/45 (2013.01)] 16 Claims
OG exemplary drawing
 
8. A circuit comprising:
an error correction code (ECC) calculation circuit that calculates an ECC having ECC bits computed using a plurality of bits pointing to a memory address, a plurality of bits representative of data stored in each memory address, and a plurality of received pad bits; wherein the plurality of memory address bits, the plurality of bits representative of the data, the plurality of received pad bits and the ECC bits define a bit pattern;
a syndrome calculation circuit that generates a plurality of syndrome values each associated with a different one of the ECC bits, the address bits and the data bits;
wherein a syndrome value of the plurality of syndrome values is associated with a respective bit in the bit pattern, and
wherein the syndrome value corresponds to a plurality of syndrome value bits; and
a comparator that detects an error in the address bits or the data bits using a subset of bits representing a maximum of the plurality of syndrome values.