US 12,191,878 B2
Signal processing circuit
Takahiko Bando, Tokyo (JP); Heisuke Nakashima, Tokyo (JP); and Fumihiro Inoue, Tokyo (JP)
Assigned to MINEBEA MITSUMI Inc., Nagano (JP)
Appl. No. 17/995,329
Filed by MINEBEA MITSUMI Inc., Nagano (JP)
PCT Filed Mar. 30, 2021, PCT No. PCT/JP2021/013488
§ 371(c)(1), (2) Date Oct. 3, 2022,
PCT Pub. No. WO2021/205939, PCT Pub. Date Oct. 14, 2021.
Claims priority of application No. 2020-070473 (JP), filed on Apr. 9, 2020.
Prior Publication US 2023/0155601 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/12 (2006.01); H03M 1/18 (2006.01)
CPC H03M 1/1245 (2013.01) [H03M 1/181 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A signal processing circuit comprising:
a first sampling capacitor and a second sampling capacitor that are connected for an input signal path of an analog signal;
an offset adjustment circuit, and
a signal processor configured to perform predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor,
wherein the sampling of the analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel,
wherein the signal processor is an amplifier and the predetermined processing is amplification processing using a feedback capacitor, and
wherein the offset adjustment circuit is provided in a stage prior to the amplifier and is configured to adjust an offset amount of the analog signal to be amplified by the amplifier.