US 12,191,877 B2
Multi-bit voltage-to-delay conversion in data converter circuitry
Sai Aditya Nurani, Bengaluru (IN); Rishi Soundararajan, Bangalore (IN); Nithin Gopinath, Bangalore (IN); Visvesvaraya Pentakota, Bangalore (IN); and Shagun Dusad, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 30, 2022, as Appl. No. 17/898,844.
Prior Publication US 2024/0072820 A1, Feb. 29, 2024
Int. Cl. H03M 1/12 (2006.01); H03M 1/44 (2006.01); H03M 1/50 (2006.01); H03M 1/78 (2006.01)
CPC H03M 1/1245 (2013.01) [H03M 1/44 (2013.01); H03M 1/50 (2013.01); H03M 1/785 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An analog-to-digital converter circuit, comprising:
a multi-bit input buffer having a differential input adapted to receive a differential input sample, and configured to generate, at a plurality of differential outputs, a plurality of residues of the input sample relative to a corresponding plurality of zero-crossing references;
a plurality of zero-crossing comparators, each having a differential input adapted to receive one of the residues from one of the differential outputs of the input buffer and having an output, each zero-crossing comparator associated with a zone threshold according to an ordered sequence of zone thresholds;
a plurality of chopping stages, each coupled to an output of the input stage and to the differential input of a corresponding comparator, and having an input adapted to receive a chop signal;
folding logic circuitry, having a plurality of inputs, each coupled to the output of one of the comparators, and configured to output a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold; and
digital stage circuitry coupled to outputs of the zero-crossing comparators and to outputs of the folding logic circuitry, the digital stage circuitry configured to generate a digital output word corresponding to the received input sample.