US 12,191,871 B2
Methods and devices for TDC resolution improvement
Evgeny Shumaker, Nesher (IL); Elan Banin, Raanana (IL); Ofir Degani, Haifa (IL); and Gil Horovitz, Emek-Hefer (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,217.
Claims priority of provisional application 63/154,884, filed on Mar. 1, 2021.
Prior Publication US 2022/0278690 A1, Sep. 1, 2022
Int. Cl. H03L 7/24 (2006.01); G04F 10/00 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/24 (2013.01) [G04F 10/005 (2013.01); H03L 7/085 (2013.01); H03L 7/0991 (2013.01); H03L 2207/50 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A time to digital converter (TDC) circuit configured to:
receive a reference clock (REF) signal and a signal derived from a local oscillator (LO);
generate a plurality of digital values based on one or more TDC measurements by a single TDC measurement component, wherein the plurality of digital values are indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined by one of a plurality of sets of TDC measurement component quantization levels;
generate a combined series of quantization levels, wherein each quantization level of the combined series of quantization levels is a sum of simultaneously-in-time occurring ones of the plurality of sets of TDC measurement component quantization levels; and
determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit.