US 12,191,865 B2
Phase lock loop (PLL) synchronization
David Francois Jacquet, Vaulnaveys le Haut (FR); Mostafa Ghazali, Grenoble (FR); Masoud Kahrizi, Irvine, CA (US); and Andras Tantos, Bellevue, WA (US)
Assigned to Space Exploration Technologies Corp., Hawthorne, CA (US)
Filed by Space Exploration Technologies Corp., Hawthorne, CA (US); and Iliana Ghazali
Filed on Jul. 24, 2023, as Appl. No. 18/225,477.
Application 18/225,477 is a continuation of application No. 17/714,081, filed on Apr. 5, 2022, granted, now 11,711,084.
Application 17/714,081 is a continuation of application No. 17/401,208, filed on Aug. 12, 2021, granted, now 11,329,653, issued on May 10, 2022.
Application 17/401,208 is a continuation of application No. 16/858,675, filed on Apr. 26, 2020, granted, now 11,133,806, issued on Sep. 28, 2021.
Claims priority of provisional application 62/982,998, filed on Feb. 28, 2020.
Claims priority of provisional application 62/847,833, filed on May 14, 2019.
Prior Publication US 2023/0378960 A1, Nov. 23, 2023
Int. Cl. H03L 7/07 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/07 (2013.01) [H03L 7/1976 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal; and
a phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal, wherein one or more timing components are configured to generate a synchronization signal to trigger phase synchronization of the PLL if the reference time signal equals a pre-set reference time signal count value and the PLL is in a locked state.