a duty cycle adjustment circuit configured to receive a signal, wherein, during a coarse adjustment selection operation, the duty cycle adjustment circuit is configured to select a coarse adjustment value to adjust a duty cycle of the signal by a coarse adjustment amount, wherein, after selection of the course adjustment value and during a fine adjustment selection operation, the duty cycle adjustment circuit is further configured to select a fine adjustment value to additionally adjust the duty cycle of the signal a fine adjustment amount to provide a duty cycle adjusted signal, wherein the duty cycle adjustment circuit comprises a first plurality of serially-coupled adjustor cells each configured to apply at least a portion of the fine adjustment amount and at least a portion of the coarse adjustment amount to the signal based on the fine adjustment value and the coarse adjustment value, respectively, wherein the duty cycle adjustment circuit further comprises a second plurality of serially-coupled adjustor cells each configured to selectively apply only a portion of the coarse adjustment amount to the signal based on the coarse adjustment value, wherein a first one of the first plurality of serially-coupled adjustor cells is configured to receive the signal simultaneous with receipt of the signal at a first one of the second of serially-coupled adjustor cells, wherein an adjustor cell of the first plurality of serially-coupled adjuster cells comprises a first transistor having a first size for providing a coarse adjustment and a second transistor having a second size for providing a fine adjustment, wherein the first size and the second size are different,

wherein the duty cycle adjustment circuit is enabled by a control signal provided by a memory controller in communication with the DRAM.