digital to analog converter configured to, responsive to a control code, output a first value and a second value, wherein the first value is different than the second value;

a first current mirror configured to generate a first current that is proportional to the first value;

a second current mirror configured to generate a second current that is proportional to the second value;

a first FET pair comprising a first FET, with a first gate terminal receiving a clock signal, and a second FET having second gate terminal receiving an inverted clock signal such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror to receive the first current;

a second FET pair comprising a third FET, with a third gate terminal receiving the inverted clock signal, and a fourth FET having fourth gate terminal receiving the clock signal such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror to receive the second current, wherein the clock signal and the inverted clock signal are the only clock signals provide to gates terminals of FET pairs in the phase interpolator;

a first output terminal, configured to output a phase adjusted clock signal as compared to the clock signal, connected to a first drain terminal of the first FET and a third drain terminal of the third FET;

a second output terminal, configured to output an inverted version of the phase adjusted clock signal, connected to a second drain terminal of the second FET and a fourth drain terminal of the fourth FET.