US 12,191,856 B2
Input buffer circuit and semiconductor system including the same
In Seok Kong, Icheon-si (KR); Jae Hyeong Hong, Icheon-si (KR); and Min Su Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 9, 2023, as Appl. No. 18/107,934.
Claims priority of application No. 10-2022-0079733 (KR), filed on Jun. 29, 2022.
Prior Publication US 2024/0007108 A1, Jan. 4, 2024
Int. Cl. H03K 19/0185 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 19/00384 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An input buffer circuit comprising:
a signal input circuit configured to receive an input signal to generate an output signal based on a reference voltage and an activation current; and
a linear setting circuit configured to compare a voltage of a first modeling node, which corresponds to the input signal, with a voltage of a second modeling node, which corresponds to the reference voltage, to generate a bias voltage for controlling the activation current.