US 12,191,823 B2
Parallel cascode amplifier for enhanced low-power mode efficiency
Philip John Lehtola, Cedar Rapids, IA (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by SKYWORKS SOLUTIONS, INC., Irvine, CA (US)
Filed on Oct. 24, 2023, as Appl. No. 18/493,287.
Application 18/493,287 is a continuation of application No. 17/578,631, filed on Jan. 19, 2022, granted, now 11,831,284.
Application 17/578,631 is a continuation of application No. 16/586,723, filed on Sep. 27, 2019, granted, now 11,264,958, issued on Mar. 1, 2022.
Claims priority of provisional application 62/738,987, filed on Sep. 28, 2018.
Prior Publication US 2024/0162865 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 3/213 (2006.01); H03F 1/02 (2006.01)
CPC H03F 3/213 (2013.01) [H03F 1/0205 (2013.01); H03F 2200/222 (2013.01); H03F 2200/249 (2013.01); H03F 2200/451 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A power amplification system comprising:
a current source;
an input switch configured to alternatively feed current from the current source to a high-power circuit path and a low-power circuit path, the high-power circuit path including a first transistor including a first collector, a first emitter, and a first base, a second transistor including a second collector, a second emitter, and a second base, and a fourth transistor including a fourth collector, a fourth emitter, and a fourth base, the first base being coupled to the second base and the first collector being coupled to the second collector, the low-power circuit path including a third transistor including a third collector, a third emitter, and a third base; and
a band switch including a switch arm for switching between a plurality of bands, each of the first collector and the second collector being coupled to the switch arm, and the third collector being coupled to the switch arm via the first transistor.