an input node that receives input signals;

an output node that generates amplified output signals;

a complementary differential NMOS transistor pair of MN1 and MN2, wherein MN1 gate and MN2 gate are coupled to the input node, and MN1 drain and MN2 drain are coupled to the output node, wherein the differential transistor pair has a capacitor Cgs,n; and

a cross-coupled PMOS transistor pair of MP1 and MP2, wherein the gate of MP1 is coupled to the gate of MN1 and the drain of MP2, and the gate of MP2 is couple to the gate of MN2 and the drain of MP1, wherein the PMOS transistor pair has a capacitor Cgs,p to improve linearity of the power amplifier.