US 12,191,815 B2
Sub-micron CMOS high-power cascode RF power amplifier
Morteza Abbasi, Vista, CA (US); Tumay Kanar, Carlsbad, CA (US); and Naveen Krishna Yanduru, San Diego, CA (US)
Assigned to Renesas Electronics America Inc., Milpitas, CA (US)
Filed by Renesas Electronics America Inc., Milpitas, CA (US)
Filed on Aug. 19, 2021, as Appl. No. 17/406,388.
Claims priority of provisional application 63/076,980, filed on Sep. 11, 2020.
Prior Publication US 2022/0085767 A1, Mar. 17, 2022
Int. Cl. H03F 1/22 (2006.01); H01Q 3/36 (2006.01); H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01); H03F 3/45 (2006.01)
CPC H03F 1/223 (2013.01) [H01Q 3/36 (2013.01); H03F 1/0211 (2013.01); H03F 3/195 (2013.01); H03F 3/245 (2013.01); H03F 3/45179 (2013.01); H03F 2200/451 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor comprising a gate having a gate oxide with a first thickness and a first gate length, the first transistor being configured as a common source amplifier stage;
a second transistor comprising a gate having a gate oxide with a second thickness and a second gate length, the second transistor being configured as a common gate amplifier stage;
a metal strip disposed on top of a gate of the first transistor; and
a set of vias placed on the metal strip to tap the gate of the first transistor,
wherein:
the set of vias are placed at points along the metal strip and outside of active regions of the first transistor;
the first transistor and the second transistor are connected in a cascode configuration;
the second thickness is greater than the first thickness; and
the second gate length is greater than the first gate length.