US 12,191,401 B2
Manufacturing method for semiconductor structure having a plurality of fins
Chia-Ming Hsu, Hualien County (TW); Yi-Jing Li, Hsinchu (TW); Chih-Hsin Ko, Kaohsiung (TW); Kuang-Hsin Chen, Taoyuan (TW); Da-Wen Lin, Hsinchu (TW); and Clement Hsingjen Wann, Carmel, NY (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jan. 18, 2024, as Appl. No. 18/415,702.
Application 18/415,702 is a division of application No. 17/357,997, filed on Jun. 25, 2021, granted, now 11,916,151.
Prior Publication US 2024/0194794 A1, Jun. 13, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a semiconductor stack having at least one SiGe layer;
forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion;
forming a poly gate stripe orthogonally over the plurality of fins;
forming a recess on each of the plurality of fins abutting the poly gate stripe;
recessing the SiGe portion by a second etching operation through the recess;
forming a first spacer and a second spacer to surround the SiGe portion; and
removing the SiGe portion.