US 12,191,399 B2
Semiconductor device and manufacturing method thereof
Tetsuhiro Tanaka, Tokyo (JP); Mitsuhiro Ichijo, Kanagawa (JP); Toshiya Endo, Kanagawa (JP); Akihisa Shimomura, Kanagawa (JP); Yuji Egi, Kanagawa (JP); Sachiaki Tezuka, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Apr. 19, 2023, as Appl. No. 18/136,431.
Application 18/136,431 is a continuation of application No. 17/167,286, filed on Feb. 4, 2021, granted, now 11,646,378.
Application 17/167,286 is a continuation of application No. 16/044,600, filed on Jul. 25, 2018, granted, now 10,923,600, issued on Feb. 16, 2021.
Application 16/044,600 is a continuation of application No. 15/092,956, filed on Apr. 7, 2016, granted, now 10,056,497, issued on Aug. 21, 2018.
Claims priority of application No. 2015-083163 (JP), filed on Apr. 15, 2015; and application No. 2015-110541 (JP), filed on May 29, 2015.
Prior Publication US 2023/0361219 A1, Nov. 9, 2023
Int. Cl. H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/78606 (2013.01); H01L 29/78648 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a first transistor, a second transistor, and a capacitor, the semiconductor device comprising:
a first insulating film over a substrate;
a first semiconductor layer including silicon over the first insulating film;
a second insulating film over the first semiconductor layer;
a first conductive layer over the second insulating film;
a third insulating film over the first conductive layer;
a second semiconductor layer including an oxide semiconductor over the third insulating film;
a fourth insulating film over the second semiconductor layer;
a second conductive layer over the fourth insulating film; and
a third conductive layer below the second semiconductor layer,
wherein the first conductive layer is configured to be a gate electrode of the first transistor,
wherein the second conductive layer is configured to be a first gate electrode of the second transistor,
wherein the third conductive layer is configured to be a second gate electrode of the second transistor,
wherein the first semiconductor layer is in electrical contact with the second semiconductor layer through a fourth conductive layer,
wherein the fourth conductive layer is in contact with one of a source and a drain of the second semiconductor layer,
wherein the fourth conductive layer has a region provided over the second conductive layer,
wherein a fifth conductive layer is in contact with the other of the source and the drain of the second semiconductor layer,
wherein the fifth conductive layer is configured to be one electrode of the capacitor, and
wherein the second semiconductor layer overlaps the first semiconductor layer in a region where the first conductive layer and the third conductive layer do not overlap each other.