US 12,191,395 B2
Dual gate control for trench shaped thin film transistors
Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); Gilbert Dewey, Hillsboro, OR (US); Jack T. Kavalieros, Portland, OR (US); Shriram Shivaraman, Hillsboro, OR (US); Benjamin Chu-Kung, Portland, OR (US); Yih Wang, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 25, 2023, as Appl. No. 18/494,384.
Application 18/494,384 is a division of application No. 17/492,487, filed on Oct. 1, 2021, granted, now 11,862,728.
Application 17/492,487 is a continuation of application No. 15/938,153, filed on Mar. 28, 2018, granted, now 11,183,594, issued on Nov. 23, 2021.
Prior Publication US 2024/0055531 A1, Feb. 15, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/78642 (2013.01) [H01L 21/02647 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/6656 (2013.01); H01L 29/6675 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10B 12/50 (2023.02); H01L 21/31116 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a thin film transistor structure, comprising:
forming a trench extending through a source and drain material layer, a first semiconductor layer, and a dielectric layer to expose a surface of a first gate dielectric layer, wherein the first gate dielectric layer is over a first gate electrode;
growing a second semiconductor layer from the first semiconductor layer and over the dielectric layer and the surface of the first gate dielectric layer to form a non-planar semiconductor layer having a portion over the surface of the first gate dielectric layer;
disposing a second gate dielectric layer over the portion of the non-planar semiconductor layer; and
disposing a second gate electrode at least partially within the trench, wherein the second gate dielectric layer is between the portion of the non-planar semiconductor layer and the second gate electrode.