US 12,191,388 B2
Area scaling for VTFET contacts
Yann Mignot, Slingerlands, NY (US); Su Chen Fan, Cohoes, NY (US); Jing Guo, Niskayuna, NY (US); and Lijuan Zou, Slingerlands, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 8, 2021, as Appl. No. 17/520,812.
Prior Publication US 2023/0145135 A1, May 11, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 29/0847 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vertical transport field effect transistor (VTFET) device, comprising:
at least one fin serving as a vertical fin channel;
a bottom source/drain region present at a base of the at least one fin;
a gate stack alongside the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin;
a top source/drain region present at a top of the at least one fin;
an encapsulation layer located on top of and along a vertical side of the gate stack that extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer is located adjacent to the top source/drain region;
a bottom spacer located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
a bottom source/drain contact to the bottom source/drain region; and
a gate contact to the gate stack, wherein the bottom source drain contact and the gate contact each comprises a single solid structure with a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion.