US 12,191,374 B2
Semiconductor device with reduced flicker noise
Hsin-Li Cheng, Hsin Chu (TW); Liang-Tai Kuo, Zhudong Township (TW); and Yu-Chi Chang, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,457.
Application 16/732,397 is a division of application No. 16/117,166, filed on Aug. 30, 2018, granted, now 10,529,818, issued on Jan. 7, 2020.
Application 18/323,457 is a continuation of application No. 17/198,626, filed on Mar. 11, 2021, granted, now 11,688,789.
Application 17/198,626 is a continuation of application No. 16/732,397, filed on Jan. 2, 2020, granted, now 10,971,596, issued on Apr. 6, 2021.
Claims priority of provisional application 62/703,636, filed on Jul. 26, 2018.
Prior Publication US 2023/0299171 A1, Sep. 21, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/3115 (2006.01); H01L 21/324 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/513 (2013.01) [H01L 21/31155 (2013.01); H01L 21/324 (2013.01); H01L 29/66492 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate electrode disposed on a substrate;
source/drain regions disposed on or within the substrate along opposing sides of the gate electrode;
a noise reducing component arranged along an upper surface of the gate electrode and/or along an upper surface of the substrate over the source/drain regions;
a cap layer covering the upper surface of the gate electrode and/or the upper surface of the substrate over the source/drain regions; and
an inter-level dielectric (ILD) disposed over and along one or more sidewalls of the cap layer.