US 12,191,370 B2
Semiconductor device with tunable channel layer usage and methods of fabrication thereof
Bo-Yu Lai, Taipei (TW); Wei-Yang Lee, Taipei (TW); Ming-Lung Cheng, Kaohsiung County (TW); Chia-Pin Lin, Hsinchu County (TW); and Yuan-Ching Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 6, 2022, as Appl. No. 17/714,528.
Claims priority of provisional application 63/289,493, filed on Dec. 14, 2021.
Prior Publication US 2023/0187518 A1, Jun. 15, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/41775 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a stack of channel layers and sacrificial layers on a substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly disposed in a vertical direction;
patterning the stack to form a semiconductor fin;
forming an isolation feature on sidewalls of the semiconductor fin;
recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature;
growing a base epitaxial layer from the recessed top surface of the semiconductor fin;
depositing an insulation layer in the source/drain recess, wherein the insulation layer is above the base epitaxial layer and above a bottommost channel layer; and
forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer.