US 12,191,332 B2
Image sensor and semiconductor device including asymmetric active region
Taeyoung Song, Hwaseong-si (KR); Sung In Kim, Hwaseong-si (KR); and Haesung Jung, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 15, 2021, as Appl. No. 17/526,424.
Claims priority of application No. 10-2020-0187337 (KR), filed on Dec. 30, 2020.
Prior Publication US 2022/0208818 A1, Jun. 30, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/778 (2023.01)
CPC H01L 27/14616 (2013.01) [H01L 27/14603 (2013.01); H01L 27/1463 (2013.01); H04N 25/778 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a first device isolation part in a substrate and defining a structured active region;
a first gate electrode that extends in a first direction across the active region and has a first gate sidewall and a second gate sidewall that are spaced apart from each other in a second direction orthogonal to the first direction; and
a first impurity region and a second impurity region disposed in the active region and respectively disposed at the first gate sidewall and the second gate sidewall,
wherein the active region includes:
a first active central part that overlaps the first gate electrode;
a first active protrusion in which the first impurity region is disposed; and
a second active protrusion in which the second impurity region is disposed,
wherein the first device isolation part has a first isolation sidewall overlapping the first active central part, wherein the first isolation sidewall extends parallel to the second direction,
wherein a first straight line is at least partially spaced apart from the first isolation sidewall, wherein the first straight line links a first point to a second point, wherein the first point is where the first active protrusion meets the first active central part and is adjacent to the first isolation sidewall, and the second point is where the second active protrusion meets the first active central part and is adjacent to the first isolation sidewall, and
wherein the first isolation sidewall vertically overlaps the first gate electrode.