US 12,191,322 B2
Semiconductor device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Feb. 9, 2024, as Appl. No. 18/437,410.
Application 18/437,410 is a continuation of application No. 18/096,045, filed on Jan. 12, 2023, granted, now 11,901,377.
Application 18/096,045 is a continuation of application No. 17/673,958, filed on Feb. 17, 2022, granted, now 11,557,613, issued on Jan. 17, 2023.
Application 17/673,958 is a continuation of application No. 17/169,602, filed on Feb. 8, 2021, granted, now 11,257,853, issued on Feb. 22, 2022.
Application 17/169,602 is a continuation of application No. 16/699,863, filed on Dec. 2, 2019, granted, now 10,916,571, issued on Feb. 9, 2021.
Application 16/699,863 is a continuation of application No. 16/417,864, filed on May 21, 2019, granted, now 10,497,723, issued on Dec. 3, 2019.
Application 16/417,864 is a continuation of application No. 15/795,321, filed on Oct. 27, 2017, granted, now 10,304,872, issued on May 28, 2019.
Application 15/795,321 is a continuation of application No. 15/247,995, filed on Aug. 26, 2016, granted, now 9,806,107, issued on Oct. 31, 2017.
Application 15/247,995 is a continuation of application No. 14/594,256, filed on Jan. 12, 2015, granted, now 9,432,016, issued on Aug. 30, 2016.
Application 14/594,256 is a continuation of application No. 14/222,822, filed on Mar. 24, 2014, granted, now 8,941,416, issued on Jan. 27, 2015.
Application 14/222,822 is a continuation of application No. 13/606,440, filed on Sep. 7, 2012, granted, now 8,736,315, issued on May 27, 2014.
Claims priority of application No. 2011-217150 (JP), filed on Sep. 30, 2011.
Prior Publication US 2024/0266369 A1, Aug. 8, 2024
Int. Cl. H01L 27/12 (2006.01); G09G 3/14 (2006.01); G09G 3/32 (2016.01); G09G 3/36 (2006.01); G11C 19/00 (2006.01); H01L 29/786 (2006.01); H03B 1/00 (2006.01); H03K 3/00 (2006.01); H03K 17/687 (2006.01)
CPC H01L 27/1255 (2013.01) [G09G 3/14 (2013.01); G09G 3/32 (2013.01); G09G 3/36 (2013.01); G11C 19/00 (2013.01); H01L 29/7869 (2013.01); H03B 1/00 (2013.01); H03K 3/00 (2013.01); H03K 17/6871 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01)] 3 Claims
OG exemplary drawing
 
2. A semiconductor device comprising:
a shift register circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the sixth transistor, and a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor, one of a source and a drain of the fourth transistor, and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the third transistor, one of a source and a drain of the seventh transistor, and one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the fourth transistor and a third wiring,
wherein a gate of the fifth transistor is electrically connected to a fourth wiring,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the ninth transistor, and
wherein a gate of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor and one of a source and a drain of the eleventh transistor.