US 12,191,316 B2
Semiconductor device
Tatsuya Toda, Tokyo (JP); Toshinari Sasaki, Tokyo (JP); and Masayoshi Fuchi, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Feb. 13, 2024, as Appl. No. 18/439,855.
Application 18/439,855 is a continuation of application No. 17/031,999, filed on Sep. 25, 2020, granted, now 11,935,898.
Application 17/031,999 is a continuation of application No. PCT/JP2019/007661, filed on Feb. 27, 2019.
Claims priority of application No. 2018-067326 (JP), filed on Mar. 30, 2018.
Prior Publication US 2024/0258331 A1, Aug. 1, 2024
Int. Cl. H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); H10K 59/12 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01)
CPC H01L 27/124 (2013.01) [G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); H01L 27/1259 (2013.01); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/131 (2023.02); G02F 1/136295 (2021.01); G09G 2300/0861 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H10K 59/1201 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate electrode;
a first gate insulating layer above the first gate electrode;
a first oxide semiconductor layer above the first gate insulating layer;
a source electrode and a drain electrode connected to the first oxide semiconductor layer;
a second gate insulating layer above the first oxide semiconductor layer;
a second gate electrode above the second gate insulating layer;
a first insulating layer above the second gate electrode;
a second oxide semiconductor layer between the second gate insulating layer and the second gate electrode;
a first aperture penetrating the first insulating layer and the second gate insulating layer, a part of the first aperture overlapping the second oxide semiconductor layer in a planar view;
a first connecting electrode in the first aperture;
a second aperture penetrating the first gate insulating layer; and
a second connecting electrode in the second aperture,
wherein
the first connecting electrode is connected to the second gate electrode and the second connecting electrode, and
the second connecting electrode is connected to the first gate electrode.